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				<h2>1.3 Verilog 门延迟</h2>				<h3><em>分类</em> <a href="../w3cnote_genre/verilog2" title="Verilog 教程高级篇" >Verilog 教程高级篇</a> </h3>
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					<h3>关键词： 门延迟， D 触发器</h3><hr>
<h2>门延迟类型</h2>
<p>前两节中所介绍的门级电路都是没有延迟的，实际门级电路都是有延迟的。</p>
<p>
Verilog 中允许用户使用门延迟，来定义输入到其输出信号的传输延迟。</p>
<p>
门延迟类型主要有以下 3 种。</p>

<h3>上升延迟</h3>
<p>在门的输入发生变化时，门的输出从 0，x，z 变化为 1 所需要的转变时间，称为上升延迟。</p>

<p><img decoding="async" src="https://www.runoob.com/wp-content/uploads/2021/05/verilog-gate-delay-1.png"></p>

<h3>下降延迟</h3><p>
在门的输入发生变化时，门的输出从 1，x，z 变化为 0 所需要的转变时间，称为下降延迟。</p>

<p><img decoding="async" src="https://www.runoob.com/wp-content/uploads/2021/05/verilog-gate-delay-2.png"></p>

<h3>关断延迟</h3><p>
关断延迟是指门的输出从 0，1，x 变化为高阻态 z 所需要的转变时间。</p>

<p><img decoding="async" src="https://www.runoob.com/wp-content/uploads/2021/05/verilog-gate-delay-3.png"></p>
<p>
门输出从 0，1，z 变化到 x 所需要的转变时间并没有被明确的定义，但是它所需要的时间可以由其他延迟类型确定，即为以上 3 种延迟值中最小的那个延迟。</p>
<p>
门延迟可以在门单元例化时定义，定义格式如下：</p>

<pre>gate_type [delay]  [instance_name]  (signal_list) ;</pre>
<p>
其中，delay 的个数可以为 0 个、1 个、2 个或 3个 。</p>
<p>
下表为不同延迟个数时，各种类型延迟的取值情况说明。</p>
<table class="tecspec"><thead><tr><th style="text-align:center;"><span>延迟类型</span></th><th style="text-align:left;"><span>无延迟</span></th><th style="text-align:center;"><span>1 个延迟 (d)</span></th><th style="text-align:left;"><span>2 个延迟 (d1, d2)</span></th><th style="text-align:center;"><span>3 个延迟 (d1, d2, d3)</span></th></tr></thead><tbody><tr><td style="text-align:center;"><span>上升</span></td><td style="text-align:left;"><span>0</span></td><td style="text-align:center;"><span>d</span></td><td style="text-align:left;"><span>d1</span></td><td style="text-align:center;"><span>d1</span></td></tr><tr><td style="text-align:center;"><span>下降</span></td><td style="text-align:left;"><span>0</span></td><td style="text-align:center;"><span>d</span></td><td style="text-align:left;"><span>d2</span></td><td style="text-align:center;"><span>d2</span></td></tr><tr><td style="text-align:center;"><span>关断</span></td><td style="text-align:left;"><span>0</span></td><td style="text-align:center;"><span>d</span></td><td style="text-align:left;"><span>min(d1, d2)</span></td><td style="text-align:center;"><span>d3</span></td></tr><tr><td style="text-align:center;"><span>to_x</span></td><td style="text-align:left;"><span>0</span></td><td style="text-align:center;"><span>d</span></td><td style="text-align:left;"><span>min(d1, d2)</span></td><td style="text-align:center;"><span>min(d1, d2, d3)</span></td></tr></tbody></table>
<p>
如果用户没有指定延迟值，则默认延迟为 0 。</p><p>
如果用户指定了 1 个延迟值，则所有类型的延迟值大小均为此值。</p><p>
如果用户指定了 2 个延迟值，则他们分别代表上升延迟和下降延迟，关断和"to_x"延迟均为这 2 种延迟值中最小的那个。</p><p>
如果用户指定了 3 个延迟值，则他们分别代表上升延迟、下降延迟和关断延迟，"to_x"延迟为这 3 种延迟值中最小的那个。</p><p>
带有延迟值的门级单元例化如下：</p>

<div class="example"><h2 class="example">实例</h2> <div class="example_code">
&nbsp; &nbsp;<span style="color: #00008B; font-style: italic;">//rise, fall and turn-off delay are all 1</span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">and</span> <span style="color: #5D478B;">#</span><span style="color: #9F79EE;">&#40;</span><span style="color: #ff0055;">1</span><span style="color: #9F79EE;">&#41;</span> &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; <span style="color: #9F79EE;">&#40;</span>OUT1<span style="color: #5D478B;">,</span> IN1<span style="color: #5D478B;">,</span> IN2<span style="color: #9F79EE;">&#41;</span> <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp;<span style="color: #00008B; font-style: italic;">//rise delay = 2.1, fall dalay = 2, trun-off delay = 2</span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">or</span> &nbsp;<span style="color: #5D478B;">#</span><span style="color: #9F79EE;">&#40;</span><span style="color: #ff0055;">2.1</span><span style="color: #5D478B;">,</span> <span style="color: #ff0055;">2</span><span style="color: #9F79EE;">&#41;</span> &nbsp; &nbsp; &nbsp; &nbsp;<span style="color: #9F79EE;">&#40;</span>OUT2<span style="color: #5D478B;">,</span> IN1<span style="color: #5D478B;">,</span> IN2<span style="color: #9F79EE;">&#41;</span> <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp;<span style="color: #00008B; font-style: italic;">//rise delay = 2, fall dalay = 1, trun-off delay = 1.3</span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">bufif0</span> <span style="color: #5D478B;">#</span><span style="color: #9F79EE;">&#40;</span><span style="color: #ff0055;">2</span><span style="color: #5D478B;">,</span> <span style="color: #ff0055;">1</span><span style="color: #5D478B;">,</span> <span style="color: #ff0055;">1.3</span><span style="color: #9F79EE;">&#41;</span> &nbsp;<span style="color: #9F79EE;">&#40;</span>OUT3<span style="color: #5D478B;">,</span> IN1<span style="color: #5D478B;">,</span> CTRL<span style="color: #9F79EE;">&#41;</span> <span style="color: #5D478B;">;</span><br />
</div></div>
<p>需要说明的是，多输入门（如与门）和多输出门（如非门）最多只能定义 2 个延迟，因为输出不会是 z 。</p>
<p>三态门和单向开关单路（MOS 管、CMOS 管等）可以定义 3 个延迟。</p>
<p>
上下拉门级电路不会有任何的延迟，因为它表示的是一种硬件属性，上下拉状态不会发生变化，且没有输出值。</p>
<p>
双向开关（tran）在传输信号时没有延迟，不允许添加延迟定义。</p>
<p>
带有控制端的双向开关（tranif1, tranif0）在开关切换的时候，会有开或关的延迟，可以给此类双向开关指定 0 个、1 个或 2 个的延迟，例如：</p>

<div class="example"><h2 class="example">实例</h2> <div class="example_code">
&nbsp; &nbsp;<span style="color: #00008B; font-style: italic;">//turn-on and turn-off delay are all 1</span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">tranif0</span> <span style="color: #5D478B;">#</span><span style="color: #9F79EE;">&#40;</span><span style="color: #ff0055;">1</span><span style="color: #9F79EE;">&#41;</span> &nbsp; &nbsp; &nbsp; &nbsp; <span style="color: #9F79EE;">&#40;</span>inout1<span style="color: #5D478B;">,</span> inout2<span style="color: #5D478B;">,</span> CTRL<span style="color: #9F79EE;">&#41;</span><span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp;<span style="color: #00008B; font-style: italic;">//turn-on delay = 1, turn-off delay = 1.2</span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">tranif1</span> <span style="color: #5D478B;">#</span><span style="color: #9F79EE;">&#40;</span><span style="color: #ff0055;">1</span><span style="color: #5D478B;">,</span> <span style="color: #ff0055;">1.2</span><span style="color: #9F79EE;">&#41;</span> &nbsp; &nbsp;<span style="color: #9F79EE;">&#40;</span>inout3<span style="color: #5D478B;">,</span> inout4<span style="color: #5D478B;">,</span> CTRL<span style="color: #9F79EE;">&#41;</span><span style="color: #5D478B;">;</span><br />
</div></div><hr>
<h2>
最小/典型/最大延迟</h2>
<p>由于集成电路制造工艺的差异，实际电路中器件的延迟总会在一定范围内波动。Verilog 中，用户不仅可以指定 3 种类型的门延迟，还可以对每种类型的门延迟指定其最小值、典型值和最大值。在编译或仿真阶段，来选择使用哪一种延迟值，为更切实际的仿真提供了支持。</p>
<ul><li>
<strong>最小值</strong>：门单元所具有的最小延迟。
</li><li>
<strong>典型值</strong>：门单元所具有的典型延迟。
</li><li>
<strong>最大值</strong>：门单元所具有的最大延迟。
</li></ul><p>
下面通过例化实例，来说明最小、典型、最大延迟的用法。</p>

<div class="example"><h2 class="example">实例</h2> <div class="example_code">
&nbsp; &nbsp;<span style="color: #00008B; font-style: italic;">//所有的延迟类型： 最小延迟 1, 典型延迟 2, 最大延迟 3 </span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">and</span> <span style="color: #5D478B;">#</span><span style="color: #9F79EE;">&#40;</span><span style="color: #ff0055;">1</span><span style="color: #5D478B;">:</span><span style="color: #ff0055;">2</span><span style="color: #5D478B;">:</span><span style="color: #ff0055;">3</span><span style="color: #9F79EE;">&#41;</span> &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; <span style="color: #9F79EE;">&#40;</span>OUT1<span style="color: #5D478B;">,</span> IN1<span style="color: #5D478B;">,</span> IN2<span style="color: #9F79EE;">&#41;</span> <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp;<span style="color: #00008B; font-style: italic;">//上升延迟：最小延迟 1, 典型延迟 2, 最大延迟 3 </span><br />
&nbsp; &nbsp;<span style="color: #00008B; font-style: italic;">//下降延迟：最小延迟 3, 典型延迟 4, 最大延迟 5</span><br />
&nbsp; &nbsp;<span style="color: #00008B; font-style: italic;">//关断延迟：最小延迟 min(1,3), 典型延迟 min(2,4), 最大延迟 min(3,5)</span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">or</span> &nbsp;<span style="color: #5D478B;">#</span><span style="color: #9F79EE;">&#40;</span><span style="color: #ff0055;">1</span><span style="color: #5D478B;">:</span><span style="color: #ff0055;">2</span><span style="color: #5D478B;">:</span><span style="color: #ff0055;">3</span><span style="color: #5D478B;">,</span> <span style="color: #ff0055;">3</span><span style="color: #5D478B;">:</span><span style="color: #ff0055;">4</span><span style="color: #5D478B;">:</span><span style="color: #ff0055;">5</span><span style="color: #9F79EE;">&#41;</span> &nbsp; &nbsp; &nbsp; &nbsp;<span style="color: #9F79EE;">&#40;</span>OUT2<span style="color: #5D478B;">,</span> IN1<span style="color: #5D478B;">,</span> IN2<span style="color: #9F79EE;">&#41;</span> <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp;<span style="color: #00008B; font-style: italic;">//上升延迟：最小延迟 1, 典型延迟 2, 最大延迟 3 </span><br />
&nbsp; &nbsp;<span style="color: #00008B; font-style: italic;">//下降延迟：最小延迟 3, 典型延迟 4, 最大延迟 5</span><br />
&nbsp; &nbsp;<span style="color: #00008B; font-style: italic;">//关断延迟：最小延迟 2, 典型延迟 3, 最大延迟 4</span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">bufif0</span> <span style="color: #5D478B;">#</span><span style="color: #9F79EE;">&#40;</span><span style="color: #ff0055;">1</span><span style="color: #5D478B;">:</span><span style="color: #ff0055;">2</span><span style="color: #5D478B;">:</span><span style="color: #ff0055;">3</span><span style="color: #5D478B;">,</span> <span style="color: #ff0055;">3</span><span style="color: #5D478B;">:</span><span style="color: #ff0055;">4</span><span style="color: #5D478B;">:</span><span style="color: #ff0055;">5</span><span style="color: #5D478B;">,</span> <span style="color: #ff0055;">2</span><span style="color: #5D478B;">:</span><span style="color: #ff0055;">3</span><span style="color: #5D478B;">:</span><span style="color: #ff0055;">4</span><span style="color: #9F79EE;">&#41;</span> &nbsp;<span style="color: #9F79EE;">&#40;</span>OUT3<span style="color: #5D478B;">,</span> IN1<span style="color: #5D478B;">,</span> CTRL<span style="color: #9F79EE;">&#41;</span> <span style="color: #5D478B;">;</span><br />
</div></div>
<hr>
<h2>D 触发器</h2><p>
下面从门级建模的角度，对 D 触发器进行设计。</p>

<h3>SR 触发器</h3><p>
SR 触发器结构图及真值表如下所示。</p>
<ul><li>
1、当 S 为低电平，G1 输出端 Q 为高电平，并反馈到 G2 输入端。如果此时 R 为高电平，则 G2 输出端 Q' 为低电平。
</li><li>
2、R 为低电平 S 为高电平时，分析同理。
</li><li>
3、S 与 R 均为高电平时，如果 Q = 1 (Q' = 0) , 则 Q 反馈到 G2 输入端后输出 Q' 仍然为 0， Q' 反馈到 G1 输入端后输出 Q 仍然是 1，呈现稳态。如果 Q =0 (Q' = 1) 同理，Q 与 Q' 的值仍然会保持不变。即 S 与 R 均为高电平时该电路具有保持的功能。
</li><li>
4、如果 S 与 R 均为低电平，则输出 Q 与 Q' 均为高电平，不再成互补的关系。所以此种情况是禁止出现的。
</li></ul>

<p><img decoding="async" src="https://www.runoob.com/wp-content/uploads/2021/05/verilog-gate-delay-4.png"></p>
<p><img decoding="async" src="https://www.runoob.com/wp-content/uploads/2021/05/verilog-gate-delay-5.png"></p>
<h3>SR 锁存器</h3>
<p>在基本的 SR 触发器前面增加 2 个与非门，可构成带有控制端 SR 锁存器。</p>
<p>
SR 锁存器及其真值表如下所示。</p>
<ul><li>
当 EN=0 时，G3、G4 截止，SR 锁存器保持输出状态不变。
</li><li>
当 EN=1 时，与基本的 SR 触发器工作原理完全相同。
</li></ul>

<p><img decoding="async" src="https://www.runoob.com/wp-content/uploads/2021/05/verilog-gate-delay-6.png"></p>
<p><img decoding="async" src="https://www.runoob.com/wp-content/uploads/2021/05/verilog-gate-delay-7.png"></p>

<h3>D 锁存器</h3><p>
基本的 SR 触发器输入端不能同时为 0， 带有控制端的 SR 锁存器输入端不能同时为 1，否则会导致输出端 Q 与 Q' 的非互补性矛盾。</p>
<p>
为消除此种不允许的状态，在带有控制端的 SR 锁存器结构中加入取反模块，保证 2 个输入端均为相反逻辑，则形成了 D 锁存器。</p>
<p>
其结构图和真值表如下所示。</p>
<ul><li>
1、当 EN=1 时，输出状态随输入状态的改变而改变。
</li><li>
2、当 EN=0 时，输出状态保持不变。
</li></ul>

<p><img decoding="async" src="https://www.runoob.com/wp-content/uploads/2021/05/verilog-gate-delay-8.png"></p>
<p><img decoding="async" src="https://www.runoob.com/wp-content/uploads/2021/05/verilog-gate-delay-9.png"></p>
<p>
D 锁存器是一种电平触发。</p>
<p>
如果在 EN=1 的有效时间内，D 端信号发生多次翻转，则输出端 Q 也会发生多次翻转。这降低了电路的抗干扰能力，不是实际所需求的安全电路。</p>
<p>
为提高触发器的可靠性，增强电路抗干扰能力，发明了在特定时刻锁存信号的 D 触发器。</p>

<h3>D 触发器</h3>
<p>将两个 D 锁存器进行级联，时钟取反，便构成了一种简单的 D 触发器，又名 Flip-flop。</p>
<p>
其结构图和真值表如下所示。</p>

<p>第一级 D 锁存器又称为主锁存器，在 CP 为低电平时锁存。第二级 D 锁存器又称为从锁存器，时钟较主锁存器相反，在  CP 为高电平时锁存。</p>

<p><img decoding="async" src="https://www.runoob.com/wp-content/uploads/2021/05/verilog-gate-delay-10.png"></p>
<p><img decoding="async" src="https://www.runoob.com/wp-content/uploads/2021/05/verilog-gate-delay-11.png"></p>
<ul><li>
1、CP=1 时，主锁存器输出端 Qm 会和 D 端信号的变化保持一致，而从锁存器处于保持状态，输出 Qs 保持不变。
</li><li>
2、CP由高电平变为低电平时，主锁存器锁存当前 D 的状态，传递到输出端 Qm 并保持不变。而从锁存器输出端 Qs 会和 Qm 的变化保持一致。此时处于锁存状态下的主锁存器输出端 Qm 会保持不变，所以 D 触发器输出端 Qs 端得到新的 Qm 值后， 也会保持不变。
</li></ul>
<p>综上所述，D 触发器输出端 Qs 只会在时钟 CP 下降沿对 D 端进行信号的锁存，其余时间输出端信号具有保持的功能。</p>
<p>
将双级 D 锁存器展开为门级结构，如下图所示。</p>

<p><img decoding="async" src="https://www.runoob.com/wp-content/uploads/2021/05/verilog-gate-delay-12.png"></p>
<p>
对 D 触发进行门级建模，并加入门级延时，verilog 模型如下：</p>

<div class="example"><h2 class="example">实例</h2> <div class="example_code">
<span style="color: #A52A2A; font-weight: bold;">module</span> D_TRI<span style="color: #9F79EE;">&#40;</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">input</span> &nbsp; &nbsp; &nbsp; D<span style="color: #5D478B;">,</span> CP<span style="color: #5D478B;">,</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">output</span> &nbsp; &nbsp; &nbsp;Q<span style="color: #5D478B;">,</span> QR<span style="color: #9F79EE;">&#41;</span><span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">parameter</span> RISE_TIME <span style="color: #5D478B;">=</span> <span style="color: #ff0055;">0.11</span> <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">parameter</span> FALL_TIME <span style="color: #5D478B;">=</span> <span style="color: #ff0055;">0.07</span> <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp;<span style="color: #00008B; font-style: italic;">//part1, not gate</span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">wire</span> &nbsp; &nbsp; &nbsp; &nbsp; CPN<span style="color: #5D478B;">,</span> DN <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">not</span> &nbsp;<span style="color: #5D478B;">#</span><span style="color: #9F79EE;">&#40;</span>RISE_TIME<span style="color: #5D478B;">,</span> FALL_TIME<span style="color: #9F79EE;">&#41;</span> &nbsp; &nbsp; &nbsp; &nbsp; <span style="color: #9F79EE;">&#40;</span>CPN<span style="color: #5D478B;">,</span> CP<span style="color: #9F79EE;">&#41;</span><span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">not</span> &nbsp;<span style="color: #5D478B;">#</span><span style="color: #9F79EE;">&#40;</span>RISE_TIME<span style="color: #5D478B;">,</span> FALL_TIME<span style="color: #9F79EE;">&#41;</span> &nbsp; &nbsp; &nbsp; &nbsp; <span style="color: #9F79EE;">&#40;</span>DN<span style="color: #5D478B;">,</span> D<span style="color: #9F79EE;">&#41;</span><span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp;<span style="color: #00008B; font-style: italic;">//part2, master trigger</span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">wire</span> &nbsp; &nbsp; &nbsp; &nbsp; G3O<span style="color: #5D478B;">,</span> G4O <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">nand</span> <span style="color: #5D478B;">#</span><span style="color: #9F79EE;">&#40;</span>RISE_TIME<span style="color: #5D478B;">,</span> FALL_TIME<span style="color: #9F79EE;">&#41;</span> &nbsp; &nbsp; &nbsp; &nbsp; <span style="color: #9F79EE;">&#40;</span>G3O<span style="color: #5D478B;">,</span> D<span style="color: #5D478B;">,</span> CP<span style="color: #9F79EE;">&#41;</span><span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">nand</span> <span style="color: #5D478B;">#</span><span style="color: #9F79EE;">&#40;</span>RISE_TIME<span style="color: #5D478B;">,</span> FALL_TIME<span style="color: #9F79EE;">&#41;</span> &nbsp; &nbsp; &nbsp; &nbsp; <span style="color: #9F79EE;">&#40;</span>G4O<span style="color: #5D478B;">,</span> DN<span style="color: #5D478B;">,</span> CP<span style="color: #9F79EE;">&#41;</span><span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">wire</span> <span style="color: #5D478B;">#</span><span style="color: #9F79EE;">&#40;</span>RISE_TIME<span style="color: #5D478B;">,</span> FALL_TIME<span style="color: #9F79EE;">&#41;</span> &nbsp; &nbsp; &nbsp; &nbsp; G1O<span style="color: #5D478B;">,</span> G2O <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">nand</span> <span style="color: #5D478B;">#</span><span style="color: #9F79EE;">&#40;</span>RISE_TIME<span style="color: #5D478B;">,</span> FALL_TIME<span style="color: #9F79EE;">&#41;</span> &nbsp; &nbsp; &nbsp; &nbsp; <span style="color: #9F79EE;">&#40;</span>G1O<span style="color: #5D478B;">,</span> G3O<span style="color: #5D478B;">,</span> G2O<span style="color: #9F79EE;">&#41;</span><span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">nand</span> <span style="color: #5D478B;">#</span><span style="color: #9F79EE;">&#40;</span>RISE_TIME<span style="color: #5D478B;">,</span> FALL_TIME<span style="color: #9F79EE;">&#41;</span> &nbsp; &nbsp; &nbsp; &nbsp; <span style="color: #9F79EE;">&#40;</span>G2O<span style="color: #5D478B;">,</span> G4O<span style="color: #5D478B;">,</span> G1O<span style="color: #9F79EE;">&#41;</span><span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp;<span style="color: #00008B; font-style: italic;">//part3, slave trigger</span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">wire</span> &nbsp; &nbsp; &nbsp; &nbsp; G7O<span style="color: #5D478B;">,</span> G8O <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">nand</span> &nbsp;<span style="color: #5D478B;">#</span><span style="color: #9F79EE;">&#40;</span>RISE_TIME<span style="color: #5D478B;">,</span> FALL_TIME<span style="color: #9F79EE;">&#41;</span> &nbsp; &nbsp; &nbsp; &nbsp;<span style="color: #9F79EE;">&#40;</span>G7O<span style="color: #5D478B;">,</span> G1O<span style="color: #5D478B;">,</span> CPN<span style="color: #9F79EE;">&#41;</span><span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">nand</span> &nbsp;<span style="color: #5D478B;">#</span><span style="color: #9F79EE;">&#40;</span>RISE_TIME<span style="color: #5D478B;">,</span> FALL_TIME<span style="color: #9F79EE;">&#41;</span> &nbsp; &nbsp; &nbsp; &nbsp;<span style="color: #9F79EE;">&#40;</span>G8O<span style="color: #5D478B;">,</span> G2O<span style="color: #5D478B;">,</span> CPN<span style="color: #9F79EE;">&#41;</span><span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">wire</span> &nbsp; &nbsp; &nbsp; &nbsp; G5O<span style="color: #5D478B;">,</span> G6O <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">nand</span> &nbsp;<span style="color: #5D478B;">#</span><span style="color: #9F79EE;">&#40;</span>RISE_TIME<span style="color: #5D478B;">,</span> FALL_TIME<span style="color: #9F79EE;">&#41;</span> &nbsp; &nbsp; &nbsp; &nbsp;<span style="color: #9F79EE;">&#40;</span>G5O<span style="color: #5D478B;">,</span> G7O<span style="color: #5D478B;">,</span> G6O<span style="color: #9F79EE;">&#41;</span><span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">nand</span> &nbsp;<span style="color: #5D478B;">#</span><span style="color: #9F79EE;">&#40;</span>RISE_TIME<span style="color: #5D478B;">,</span> FALL_TIME<span style="color: #9F79EE;">&#41;</span> &nbsp; &nbsp; &nbsp; &nbsp;<span style="color: #9F79EE;">&#40;</span>G6O<span style="color: #5D478B;">,</span> G8O<span style="color: #5D478B;">,</span> G5O<span style="color: #9F79EE;">&#41;</span><span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">assign</span> &nbsp; &nbsp; &nbsp; Q <span style="color: #5D478B;">=</span> G5O <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">assign</span> &nbsp; &nbsp; &nbsp; QR <span style="color: #5D478B;">=</span> G6O <span style="color: #5D478B;">;</span><br />
<span style="color: #A52A2A; font-weight: bold;">endmodule</span><br />
</div></div>
<p>testbench 编写如下：</p>

<div class="example"><h2 class="example">实例</h2> <div class="example_code">
<span style="color: #008800;">`timescale</span> <span style="color: #ff0055;">1ns</span><span style="color: #5D478B;">/</span><span style="color: #ff0055;">1ps</span><br />
<span style="color: #A52A2A; font-weight: bold;">module</span> test <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">reg</span> &nbsp;D<span style="color: #5D478B;">,</span> CP <span style="color: #5D478B;">=</span> <span style="color: #ff0055;">0</span> <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">wire</span> Q<span style="color: #5D478B;">,</span> QR <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">always</span> <span style="color: #5D478B;">#</span><span style="color: #ff0055;">5</span> CP <span style="color: #5D478B;">=</span> <span style="color: #5D478B;">~</span>CP <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">initial</span> <span style="color: #A52A2A; font-weight: bold;">begin</span><br />
&nbsp; &nbsp; &nbsp; D <span style="color: #5D478B;">=</span> <span style="color: #ff0055;">0</span> <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; &nbsp; <span style="color: #5D478B;">#</span><span style="color: #ff0055;">12</span> D <span style="color: #5D478B;">=</span> <span style="color: #ff0055;">1</span> <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; &nbsp; <span style="color: #5D478B;">#</span><span style="color: #ff0055;">10</span> D <span style="color: #5D478B;">=</span> <span style="color: #ff0055;">0</span> <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; &nbsp; <span style="color: #5D478B;">#</span><span style="color: #ff0055;">14</span> D <span style="color: #5D478B;">=</span> <span style="color: #ff0055;">1</span> <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; &nbsp; <span style="color: #5D478B;">#</span><span style="color: #ff0055;">3</span> &nbsp;D <span style="color: #5D478B;">=</span> <span style="color: #ff0055;">0</span> <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; &nbsp; <span style="color: #5D478B;">#</span><span style="color: #ff0055;">18</span> D <span style="color: #5D478B;">=</span> <span style="color: #ff0055;">0</span> <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">end</span><br />
&nbsp; &nbsp;D_TRI u_d_trigger<span style="color: #9F79EE;">&#40;</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; .D &nbsp; &nbsp; &nbsp;<span style="color: #9F79EE;">&#40;</span>D<span style="color: #9F79EE;">&#41;</span><span style="color: #5D478B;">,</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; .CP &nbsp; &nbsp; <span style="color: #9F79EE;">&#40;</span>CP<span style="color: #9F79EE;">&#41;</span><span style="color: #5D478B;">,</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; .Q &nbsp; &nbsp; &nbsp;<span style="color: #9F79EE;">&#40;</span>Q<span style="color: #9F79EE;">&#41;</span><span style="color: #5D478B;">,</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; .QR &nbsp; &nbsp; <span style="color: #9F79EE;">&#40;</span>QR<span style="color: #9F79EE;">&#41;</span><span style="color: #9F79EE;">&#41;</span><span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">initial</span> <span style="color: #A52A2A; font-weight: bold;">begin</span><br />
&nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">forever</span> <span style="color: #A52A2A; font-weight: bold;">begin</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp;<span style="color: #5D478B;">#</span><span style="color: #ff0055;">100</span><span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp;<span style="color: #00008B; font-style: italic;">//$display(&quot;---gyc---%d&quot;, $time);</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">if</span> <span style="color: #9F79EE;">&#40;</span><span style="color: #9932CC;">$time</span> <span style="color: #5D478B;">&gt;=</span> <span style="color: #ff0055;">1000</span><span style="color: #9F79EE;">&#41;</span> <span style="color: #A52A2A; font-weight: bold;">begin</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; <span style="color: #9932CC;">$finish</span> <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">end</span><br />
&nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">end</span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">end</span><br />
<span style="color: #A52A2A; font-weight: bold;">endmodule</span> <span style="color: #00008B; font-style: italic;">// test</span><br />
</div></div>
<p>仿真结果如下。</p>
<p>由图可知，Q/QR 信号均在时钟 CP 下降沿采集到了 D 端信号，并在单周期内保持不变，且输出有延迟。</p>

<p><img decoding="async" src="https://www.runoob.com/wp-content/uploads/2021/05/verilog-gate-delay-13.png"></p>
<p>对 cap3 时刻进行放大，对延时进行追踪，如下图所示。</p>
<ul><li>
CP 端到 CPN 端有上升延迟，时间为 110ps；
</li><li>
CPN 端到 G8O 端有下降延迟，时间为 70ps；
</li><li>
G8O 端到 G6O 端有上升延迟，时间为 110ps；
</li><li>
G6O 端到 Q 端有下降延迟，时间为 70ps；
</li><li>
共 360ps，符合设置的门延迟。</li></ul>

<p><img decoding="async" src="https://www.runoob.com/wp-content/uploads/2021/05/verilog-gate-delay-14.png"></p>

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	<li><a target="_top" data-id="23639" title="0.1 数字逻辑设计" href="../w3cnote/verilog2-tutorial.html" >0.1 数字逻辑设计</a></li>
	
		
	<li><a target="_top" data-id="23641" title="0.2 Verilog 编码风格" href="../w3cnote/verilog2-codestyle.html" >0.2 Verilog 编码风格</a></li>
	
		
	<li><a target="_top" data-id="23644" title="0.3 Verilog 代码规范" href="../w3cnote/verilog2-codeguide.html" >0.3 Verilog 代码规范</a></li>
	
		
	<li><a target="_top" data-id="23645" title="1.1 Verilog 门的类型" href="../w3cnote/verilog2-gate.html" >1.1 Verilog 门的类型</a></li>
	
		
	<li><a target="_top" data-id="23648" title="1.2 Verilog 开关级建模" href="../w3cnote/verilog2-level-modeling.html" >1.2 Verilog 开关级建模</a></li>
	
		<li>
	1.3 Verilog 门延迟	</li>
	
		
	<li><a target="_top" data-id="23673" title="2.1 Verilog UDP 基础知识" href="../w3cnote/verilog2-udp.html" >2.1 Verilog UDP 基础知识</a></li>
	
		
	<li><a target="_top" data-id="23674" title="2.2 Verilog 组合逻辑 UDP" href="../w3cnote/verilog2-udp-logic.html" >2.2 Verilog 组合逻辑 UDP</a></li>
	
		
	<li><a target="_top" data-id="23677" title="2.3 Verilog 时序逻辑 UDP" href="../w3cnote/verilog2-udp-timing.html" >2.3 Verilog 时序逻辑 UDP</a></li>
	
		
	<li><a target="_top" data-id="23685" title="3.1 Verilog 延迟模型" href="../w3cnote/verilog2-delay-type.html" >3.1 Verilog 延迟模型</a></li>
	
		
	<li><a target="_top" data-id="23690" title="3.2 Verilog specify 块语句" href="../w3cnote/verilog2-specify.html" >3.2 Verilog specify 块语句</a></li>
	
		
	<li><a target="_top" data-id="23692" title="3.3 Verilog 建立时间和保持时间" href="../w3cnote/verilog2-setup-hold-time.html" >3.3 Verilog 建立时间和保持时间</a></li>
	
		
	<li><a target="_top" data-id="23701" title="3.4 Verilog 时序检查" href="../w3cnote/verilog2-timing-check.html" >3.4 Verilog 时序检查</a></li>
	
		
	<li><a target="_top" data-id="23708" title="3.5 Verilog 延迟反标注" href="../w3cnote/verilog2-sdf.html" >3.5 Verilog 延迟反标注</a></li>
	
		
	<li><a target="_top" data-id="23714" title="4.1 Verilog 同步与异步" href="../w3cnote/verilog-sync.html" >4.1 Verilog 同步与异步</a></li>
	
		
	<li><a target="_top" data-id="23725" title="4.2 Verilog 跨时钟域传输：慢到快" href="../w3cnote/verilog2-slow2fast.html" >4.2 Verilog 跨时钟域传输：慢到快</a></li>
	
		
	<li><a target="_top" data-id="23729" title="4.3 Verilog 跨时钟域传输：快到慢" href="../w3cnote/verilog2-fast2slow.html" >4.3 Verilog 跨时钟域传输：快到慢</a></li>
	
		
	<li><a target="_top" data-id="23731" title="4.4 Verilog FIFO 设计" href="../w3cnote/verilog2-fifo.html" >4.4 Verilog FIFO 设计</a></li>
	
		
	<li><a target="_top" data-id="23739" title="5.1 Verilog 复位简介" href="../w3cnote/verilog2-reset.html" >5.1 Verilog 复位简介</a></li>
	
		
	<li><a target="_top" data-id="23743" title="5.2 Verilog 时钟简介" href="../w3cnote/verilog2-clock.html" >5.2 Verilog 时钟简介</a></li>
	
		
	<li><a target="_top" data-id="23757" title="5.3 Verilog 时钟分频" href="../w3cnote/verilog2-clock-division.html" >5.3 Verilog 时钟分频</a></li>
	
		
	<li><a target="_top" data-id="23768" title="5.4 Verilog 时钟切换" href="../w3cnote/verilog2-clock-switch.html" >5.4 Verilog 时钟切换</a></li>
	
		
	<li><a target="_top" data-id="23779" title="6.1 Verilog 低功耗简介" href="../w3cnote/verilog2-low-power.html" >6.1 Verilog 低功耗简介</a></li>
	
		
	<li><a target="_top" data-id="23788" title="6.2 Verilog 系统级低功耗设计" href="../w3cnote/verilog2-lower-power-design.html" >6.2 Verilog 系统级低功耗设计</a></li>
	
		
	<li><a target="_top" data-id="23792" title="6.3 Verilog  RTL 级低功耗设计（上）" href="../w3cnote/verilog2-rtl-low-power-design-1.html" >6.3 Verilog  RTL 级低功耗设计（上）</a></li>
	
		
	<li><a target="_top" data-id="23796" title="6.4 Verilog RTL 级低功耗设计（下）" href="../w3cnote/verilog2-rtl-low-power-design-2.html" >6.4 Verilog RTL 级低功耗设计（下）</a></li>
	
		
	<li><a target="_top" data-id="23806" title="7.1 Verilog 显示任务" href="../w3cnote/verilog2-display.html" >7.1 Verilog 显示任务</a></li>
	
		
	<li><a target="_top" data-id="23813" title="7.2 Verilog 文件操作" href="../w3cnote/verilog2-file.html" >7.2 Verilog 文件操作</a></li>
	
		
	<li><a target="_top" data-id="23825" title="7.3 Verilog 随机数及概率分布" href="../w3cnote/verilog2-random.html" >7.3 Verilog 随机数及概率分布</a></li>
	
		
	<li><a target="_top" data-id="23847" title="7.4 Verilog 实数整数转换" href="../w3cnote/verilog2-real2int.html" >7.4 Verilog 实数整数转换</a></li>
	
		
	<li><a target="_top" data-id="23851" title="7.5 Verilog 其他系统任务" href="../w3cnote/verilog2-other-task.html" >7.5 Verilog 其他系统任务</a></li>
	
		
	<li><a target="_top" data-id="23862" title="8.1 Verilog  PLI 简介" href="../w3cnote/verilog2-pli-intro.html" >8.1 Verilog  PLI 简介</a></li>
	
		
	<li><a target="_top" data-id="23865" title="8.2 Verilog TF 子程序" href="../w3cnote/verilog2-tf.html" >8.2 Verilog TF 子程序</a></li>
	
		
	<li><a target="_top" data-id="23869" title="8.3 Verilog TF 子程序列表" href="../w3cnote/verilog2-tf-sub.html" >8.3 Verilog TF 子程序列表</a></li>
	
		
	<li><a target="_top" data-id="23870" title="8.4 Verilog ACC 子程序" href="../w3cnote/verilog2-acc.html" >8.4 Verilog ACC 子程序</a></li>
	
		
	<li><a target="_top" data-id="23872" title="8.5 Verilog ACC 子程序列表" href="../w3cnote/verilog2-acc-sub.html" >8.5 Verilog ACC 子程序列表</a></li>
	
		
	<li><a target="_top" data-id="23876" title="9.1 Verilog 逻辑综合" href="../w3cnote/verilog2-logic-sumarry.html" >9.1 Verilog 逻辑综合</a></li>
	
		
	<li><a target="_top" data-id="23882" title="9.2 Verilog 可综合性设计" href="../w3cnote/verilog2-integrated-design.html" >9.2 Verilog 可综合性设计</a></li>
	
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